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MC14514B, MC14515B 4-Bit Transparent Latch/4-to-16 Line Decoder
The MC14514B and MC14515B are two output options of a 4 to 16 line decoder with latched inputs. The MC14514B (output active high option) presents a logical "1" at the selected output, whereas the MC14515B (output active low option) presents a logical "0" at the selected output. The latches are R-S type flip-flops which hold the last input data presented prior to the strobe transition from "1" to "0". These high and low options of a 4-bit latch/4 to 16 line decoder are constructed with N-channel and P-channel enhancement mode devices in a single monolithic structure. The latches are R-S type flip-flops and data is admitted upon a signal incident at the strobe input, decoded, and presented at the output. These complementary circuits find primary use in decoding applications where low power dissipation and/or high noise immunity is desired.
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24 PDIP-24 P SUFFIX CASE 709 1
MARKING DIAGRAMS
MC145XXBCP AWLYYWW
* Supply Voltage Range = 3.0 Vdc to 18 Vdc * Capable of Driving Two Low-power TTL Loads or One Low-power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value - 0.5 to +18.0 - 0.5 to VDD + 0.5 10 500 - 55 to +125 - 65 to +150 260 Unit V V SOIC-24 DW SUFFIX CASE 751E
24 145XXB AWLYYWW 1 mA mW C C C XX = Specific Device Code A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week
ORDERING INFORMATION
Device MC14514BCP MC14514BDW MC14514BDWR2 MC14515BCP MC14515BDW MC14515BDWR2 Package PDIP-24 SOIC-24 SOIC-24 PDIP-24 SOIC-24 SOIC-24 Shipping 15/Rail 30/Rail 1000/Tape & Reel 15/Rail 30/Rail 1000/Tape & Reel
1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained (Vin or Vout) VDD. to the range VSS Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
v
v
(c) Semiconductor Components Industries, LLC, 2000
1
March, 2000 - Rev. 3
Publication Order Number: MC14514B/D
MC14514B, MC14515B
PIN ASSIGNMENT
ST D1 D2 S7 S6 S5 S4 S3 S1 S2 S0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD INH D4 D3 S10 S11 S8 S9 S14 S15 S12 S13
DECODE TRUTH TABLE (Strobe = 1)*
Data Inputs
Selected Output A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X MC14514 = Logic "1" MC14515 = Logic "0" S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 All Outputs = 0, MC14514 All Outputs = 1, MC14515
Inhibit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X
C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X
B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X
X = Don't Care *Strobe = 0, Data is latched
BLOCK DIAGRAM
VDD = PIN 24 VSS = PIN 12 DATA 1 DATA 2 DATA 3 DATA 4 STROBE 2 3 A
B TRANSPARENT 21 C LATCH 22 D
4 TO 16 DECODER
1
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15
11 9 10 8 7 6 5 4 18 17 20 19 14 13 16 15
ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD
INHIBIT
23
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MC14514B, MC14515B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 - 1.2 - 0.25 - 0.62 - 1.8 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 - 1.0 - 0.2 - 0.5 - 1.5 0.51 1.3 3.4 -- -- -- -- -- - 1.7 - 0.36 - 0.9 - 3.5 0.88 2.25 8.8 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- 0.1 7.5 5.0 10 20 - 0.7 - 0.14 - 0.35 - 1.1 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ (3.) 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current (4.) (5.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD Adc pF Adc ITL IT = (1.35 A/kHz) f + IDD IT = (2.70 A/kHz) f + IDD IT = (4.05 A/kHz) f + IDD Adc 3. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 4. The formulas given are for the typical characteristics only at 25_C. 5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.002.
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MC14514B, MC14515B
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)
Characteristic All Types Typ (7.) 180 90 65 100 50 40 550 225 150 400 150 100 125 50 38 - 100 - 40 - 30 175 50 38 Symbol tTLH VDD 5.0 10 15 tTHL 5.0 10 15 tPLH, tPHL 5.0 10 15 5.0 10 15 5.0 10 15 th 5.0 10 15 5.0 10 15 -- -- -- -- -- -- -- -- -- 250 100 75 - 20 0 10 350 100 75 200 100 80 ns 1100 450 300 ns 800 300 200 ns -- -- -- -- -- -- -- -- -- ns Min -- -- -- Max 360 180 130 ns Unit ns Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time; Data, Strobe to S tPLH, tPHL = (1.7 ns/pF) CL + 465 ns tPLH, tPHL = (0.86 ns/pF) CL + 192 ns tPLH, tPHL = (0.5 ns/pF) CL + 125 ns Inhibit Propagation Delay Times tPLH, tPHL = (1.7 ns/pF) CL + 315 ns tPLH, tPHL = (0.66 ns/pF) CL + 117 ns tPLH, tPHL = (0.5 ns/pF) CL + 75 ns Setup Time Data to Strobe tPLH, tPHL tsu Hold Time Strobe to Data Strobe Pulse Width tWH ns 6. The formulas given are for the typical characteristics only at 25_C. 7. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. VDD VDS STROBE INHIBIT For MC14514B 1. For P-channel: Inhibit = VSS 1. and D1-D4 constitute 1. binary code for "output 1. under test." 2. For N-channel: Inhibit = VDD D1 D2 D3 D4 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 VSS For MC14515B 1. For P-channel: Inhibit = VDD 2. For N-channel: Inhibit = VSS 2. and D1-D4 constitute binary 2. code for "output under test." ID EXTERNAL POWER SUPPLY
Figure 1. Drain Characteristics Test Circuit
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MC14514B, MC14515B
VDD 0.01 F CERAMIC
ID VDD 500 F
24
20 ns PULSE GENERATOR D1 S0 D2 D3 D4 STROBE INHIBIT S15
12
20 ns VDD VSS
CL
Vin
90% 10%
VSS
CL
Figure 2. Dynamic Power Dissipation Test Circuit and Waveform
VDD
STROBE INHIBIT D1 D2
S0 S1
OUTPUT S0 OUTPUT S1 CL CL
INPUT
tTLH 20 ns 90% 50%
tTHL VDD VSS tPHL VDD VSS tTHL
PROGRAMMABLE PULSE GENERATOR
10% tPLH
OUTPUT
D3 D4
S15
90% 50% 10% tTLH
OUTPUT S15 CL
VSS
Figure 3. Switching Time Test Circuit and Waveforms
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LOGIC DIAGRAM
AB CD AB CD AB CD AB CD S Q A AB CD R B Q AB CD AB CD AB CD R S Q C AB CD R S Q D Q AB CD AB CD Q AB CD
11 S0 9 S1 10 S2 8 S3 7 S4 6 S5 5 S6 4 S7 18 S8 17 S9 20 S10 19 S11 AB CD 14 S12 AB CD 13 S13 AB CD AB CD 16 S14 15 S15
DATA 1 2
DATA 2 3 S Q
MC14514B, MC14515B
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R Q
6
DATA 3 21
DATA 4 22
STROBE 1
INHIBIT 23
IN MC14515B ONLY
MC14514B, MC14515B
COMPLEX DATA ROUTING Two MC14512 eight-channel data selectors are used here with the MC14514B four-bit latch/decoder to effect a complex data routing system. A total of 16 inputs from data registers are selected and transferred via a 3-state data bus to a data distributor for rearrangement and entry into 16 output registers. In this way sequential data can be re-routed or intermixed according to patterns determined by data select and distribution inputs. Data is placed into the routing scheme via the eight inputs on both MC14512 data selectors. One register is assigned to each input. The signals on A0, A1, and A2 choose one of eight inputs for transfer out to the 3-state data bus. A fourth signal, labelled Dis, disables one of the MC14512 selectors, assuring transfer of data from only one register. In addition to a choice of input registers, 1 thru 16, the rate of transfer of the sequential information can also be varied. That is, if the MC14512 were addressed at a rate that is eight times faster then the shift frequency of the input registers, the most significant bit (MSB) from each register could be selected for transfer to the data bus. Therefore, all of the most significant bits from all of the registers can be transferred to the data bus before the next most significant bit is presented for transfer by the input registers. Information from the 3-state bus is redistributed by the MC14514B four-bit latch/decoder. Using the four-bit address, D1 thru D4, the information on the inhibit line can be transferred to the addressed output line to the desired output registers, A thru P. This distribution of data bits to the output registers can be made in many complex patterns. For example, all of the most significant bits from the input registers can be routed into output register A, all of the next most significant bits into register B, etc. In this way horizontal, vertical, or other methods of data slicing can be implemented.
DATA ROUTING SYSTEM
INPUT REGISTERS
DATA TRANSFER
3-STATE DATA BUS
DATA DISTRIBUTION
OUTPUT REGISTERS
REGISTER 1
D0 D1 D2 D3 D4 D5 D6
DIS
Q
REGISTER 8
D7 A0 A1 A2
DATA SELECT
REGISTER 9
REGISTER 16
A0 A1 A2 D0 Q D1 D2 D3 D4 D5 D6 D7 DIS MC14512
D1 D2 D3 D4 S0 STROBE S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 INHIBIT S14 S15 MC14514B
MC14512
REGISTER A
REGISTER P
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MC14514B, MC14515B
PACKAGE DIMENSIONS
PDIP-24 P SUFFIX PLASTIC DIP PACKAGE CASE 709-02 ISSUE C
J
24 13
B
1 12
L
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 1.235 1.265 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.080 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 31.37 32.13 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.03 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02
A N C
M
K H G F D
SEATING PLANE
DIM A B C D F G H J K L M N
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MC14514B, MC14515B
PACKAGE DIMENSIONS
SOIC-24 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E-04 ISSUE E
-A-
24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE X 45 _
M
22X
G
K
DIM A B C D F G J K M P R
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MC14514B, MC14515B
Notes
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MC14514B, MC14515B
Notes
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MC14514B, MC14515B
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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MC14514B/D

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